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19-2087; Rev 2; 5/03
Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873
General Description
The MAX3873 is a compact, low-power 2.488Gbps/ 2.67Gbps clock-recovery and data-retiming IC for SDH/SONET applications. The phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by this recovered clock, providing a clean data output. The MAX3873 meets all SDH/SONET jitter specifications, does not require an external reference clock to aid in frequency acquisition, and provides excellent tolerance to both deterministic and sinusoidal jitter. The MAX3873 provides a PLL loss-of-lock (LOL) output to indicate whether the CDR is in lock. The recovered data and clock outputs are CML with on-chip 50 back terminations on each line. The clock output can be powered down if not used. The MAX3873 is implemented in Maxim's second-generation SiGe process and consumes only 260mW at 3.3V supply (output clock disabled, low output swing). The device is available in a 4mm x 4mm 20-pin QFN exposed-pad package and operates from -40C to +85C.
Features
Fully Integrated Clock Recovery and Data Retiming Power Dissipation: 260mW with +3.3V Supply Clock Jitter Generation: 5mUIRMS Exceeds ANSI, ITU, and Bellcore SDH/SONET Jitter Specifications Differential Input Range: 50mVP-P to 1.6VP-P Single +3.3V Power Supply PLL Fast Track (FASTRACK) Mode Available Clock Output Can Be Disabled Input Data Rate: 2.488Gbps or 2.67Gbps Selectable Output Amplitude Tolerates 2000 Consecutive Identical Digits Loss-of-Lock Indicator Differential CML Data and Clock Outputs Operating Temperature Range: -40C to +85C
Applications
Switch Matrix Backplanes SDH/SONET Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects SDH/SONET Test Equipment DWDM Transmission Systems
MAX3873EGP PART
Ordering Information
TEMP RANGE -40C to +85C PINPACKAGE 20 QFN (4mm x 4mm) PKG. CODE G2044-3
Pin Configuration
GND FIL+ GND 17 LOL 16
FIL-
TOP VIEW
20
19
Typical Application Circuit appears at end of data sheet.
RATESET VCC SDI+ SDIVCC 1 2 3 4 5 10 15 14 13 SDO+ SDOVCC_BUF SCLKO+ SCLKO-
MAX3873
18
12 11
6
7
8
VCC_VCO
MODE
9
FASTRACK
QFN**
**NOTE: THE EXPOSED PAD MUST BE SOLDERED TO THE SUPPLY GROUND.
________________________________________________________________ Maxim Integrated Products
SCLKEN
VCC
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +5.0V Voltage at SDI .............................. (VCC - 1.0V) to (VCC + 0.5V) CML Output Current at SDO, SCLKO ............................22mA Voltage at LOL, FASTRACK, FIL, SCLKEN MODE, RATESET...................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 20-Pin QFN (derate 20.0mW/C above +85C) ........1300mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-50C to +150C Processing Temperature..................................................+400C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, TA = -40C to +85C. Typical values are at 2.488Gbps, VCC = 3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Current SYMBOL ICC CONDITIONS MODE = GND, SCLKEN = Low (Note 2) MODE = OPEN, SCLKEN = High (Note 2) (Figure 1) (Figure 1) DC-coupled (Figure 1) RIN MODE = Open (Note 3) Differential Output Swing MODE = VCC (Note 3) MODE = GND (Note 3) Differential Output Resistance Output Common-Mode Voltage RO MODE = Open (Note 3) MODE = VCC (Note 3) MODE = GND (Note 3) TTL INPUT/OUTPUT SPECIFICATIONS (FASTRACK, LOL, SCLKEN, MODE, RATESET) Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage VOH VOL IOH = sourcing 40A IOL = sinking 2mA VIH VIL -30 2.4 0.4 2.0 0.8 +30 V V A V V 50 VCC - 0.8 VCC - VID/4 40 600 400 200 80 50 660 500 330 100 VCC - 0.17 VCC - 0.13 VCC - 0.08 V 60 1000 800 600 120 mVP-P MIN TYP 79 105 1600 VCC + 0.4 MAX 99 UNITS mA
CML INPUT SPECIFICATIONS (SDI+, SDI-) Differential Input Voltage Single-Ended Input Voltage Input Common-Mode Voltage Input Termination to VCC VID VIS mVP-P V V
CML OUTPUT SPECIFICATIONS (SDO+, SDO-, SCLKO+, SCLKO-)
2
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Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, CF = 0.01F, TA = -40C to +85C. Typical values are at VCC = 3.3V, 2.488Gbps, TA = +25C, unless otherwise noted.) (Note 4)
PARAMETER Serial Input Data Rate Clock-to-Q Delay Jitter Peaking Jitter Transfer Bandwidth tCLK-Q JP JBW SYMBOL RATESET = Low RATESET = High (Figure 2) (Note 5) f 2MHz RATESET = Low f = 70kHz, 0.4UI deterministic jitter on input data Sinusoidal Jitter Tolerance (Note 6) f = 100kHz, 0.4UI deterministic jitter on input data f = 1MHz, 0.4UI deterministic jitter on input data f = 10MHz, 0.4UI deterministic jitter on input data Jitter Generation Clock Output Edge Speed Data Output Edge Speed Tolerated Consecutive Identical Digits SDI Input Return Loss (-20log(S11)) Frequency Acquisition Time LOL Assert Time 100kHz to 2.5GHz 2.5GHz to 4.0GHz (Figure 4) (Figure 4) JGEN (Note 7) (20% to 80%) (20% to 80%) 2.12 0.33 0.15 6.9 4.5 0.6 0.3 5.0 45 60 60 2000 17 14 1.0 1.6 6.8 62 110 110 mUIRMS mUIP-P ps ps bits dB ms s UIP-P -70 CONDITIONS MIN TYP 2.488 2.67 +70 0.1 2.0 MAX UNITS Gbps ps dB MHz
MAX3873
Note 1: At TA = -40C, DC characteristics are guaranteed by design and characterization. Note 2: CML outputs open. Note 3: RL = 50 to VCC. Note 4: AC characteristics are guaranteed by design and characterization. Note 5: Relative to the falling edge of SCLKO+. See Figure 2. Note 6: Measured with 223 - 1 PRBS. Note 7: Jitter BW = 12kHz to 20MHz.
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3
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873
VCC + 0.4V 800mV VCC SCLKO+ VCC - 0.4V VCC SDO 800mV VCC - 0.4V (a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL) 25mV tCLK-Q 25mV tCLK
Figure 2. Definition of Clock-to-Q Delay
VCC - 0.8V (b) DC-COUPLED SINGLE-ENDED CML INPUT
Figure 1. Definition of Input Voltage Swing
SERIAL DATA <2s
1200 BITS OF 1-0 PATTERN DATA VCO CLOCK PHASE ALIGNED TO INPUT DATA FASTRACK
Figure 3. Definition of Phase Acquisition Time
INPUT DATA
LOL ASSERT TIME LOL OUTPUT
FREQUENCY ACQUISITION TIME
Figure 4. Definition of LOL Assert Time and Frequency Acquisition Time
4
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Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
RECOVERED CLOCK AND DATA (2.488Gbps, 223 - 1 PATTERN, VIN = 50mVP-P)
MAX3873 toc01
RECOVERED CLOCK AND DATA (2.67Gbps, 223 - 1 PATTERN, VIN = 50mVP-P)
MAX3873 toc02
125mV/div
125mV/div
100ps/div
100ps/div
RECOVERED CLOCK JITTER (2.488Gbps)
MAX3873 toc03
JITTER TOLERANCE (2.488Gbps, 223 - 1 PATTERN, VIN = 50mVP-P)
MAX3873 toc04
100 WITH 0.2UI OF PWD
INPUT JITTER (UIp-p)
10
WITH 0.4UI OF DETERMINISTIC JITTER
1 BELLCORE MASK 0.1 10 100 1000 10,000
223 - 1 PATTERN RMS = 2.0psRMS 10ps/div
JITTER FREQUENCY (kHz)
JITTER TRANSFER
MAX3873 toc05
SUPPLY CURRENT vs. TEMPERATURE (SCLKO DISABLED)
MAX3873 toc06
SUPPLY CURRENT vs. TEMPERATURE (SCLKO ENABLED)
180 160 SUPPLY CURRENT (mA) 140 120 100 80 60 40 20 0 MIN OUTPUT SWING MAX OUTPUT SWING MED OUTPUT SWING
MAX3873 toc07
0.5 0 -0.5 TRANSFER (dB) -1.0 -1.5 -2.0 -2.5 -3.0 103 104 105 FREQUENCY (Hz) 106
200 180 160 SUPPLY CURRENT (mA) 140 120 100 80 60 40 20 MIN OUTPUT SWING MED OUTPUT SWING MAX OUTPUT SWING
200
BELLCORE MASK
107
0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
-50
-25
0
25
50
75
100
TEMPERATURE (C)
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5
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
PULLIN RANGE (RATESET = 0)
MAX3873 toc08
BIT ERROR RATIO vs. INPUT AMPLITUDE
10-3 10-4 BIT ERROR RATIO 10-5 10-6 10-7 10-8 10-9 10-10
MAX3873 toc09
3.0 2.9 2.8 FREQUENCY (GHz) 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -50 0 50
10-2
100
0
1
2
3
4
5
AMBIENT TEMPERATURE (C)
INPUT VOLTAGE (mVp-p)
JITTER TOLERANCE vs. INPUT DETERMINISTIC JITTER
MAX3873 toc10
JITTER TOLERANCE vs. PULSE-WIDTH DISTORTION
SINUSOIDAL JITTER TOLERANCE (UIP-P) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 INPUT DATA FILTERED BY 1870MHz 4TH-ORDER BESSEL FILTER -40 -30 -20 -10 0 10 20 30 40 fJITTER = 10MHz PRBS = 223 - 1 fJITTER = 1MHz
MAX3873 toc11
1.0 SINUSOIDAL JITTER TOLERANCE (UIP-P) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.05 0.10 0.15 PRBS = 223 - 1 fJITTER = 10MHz fJITTER = 1MHz
1.0
0.20
DETERMINISTIC JITTER (UIP-P)
INPUT PULSE-WIDTH DISTORTION (%)
Pin Description
PIN 1 2, 5, 6 3 4 7 8 9 NAME RATESET VCC SDI+ SDIFASTRACK VCC_VCO MODE 3.3V Supply Voltage Positive Serial Data Input Negative Serial Data Input PLL Fast Track Control, TTL Input. When FASTRACK is TTL high, the PLL is switched to a fasttrack mode for fast phase acquisition. When FASTRACK is TTL low, the PLL operates normally. 3.3V VCO Supply Voltage Output Amplitude Mode Select. MODE = OPEN sets the CML output amplitude to high; MODE = high sets the output amplitude to medium; MODE = low sets the output amplitude to low. FUNCTION Input Rate Select. Connect to TTL low for 2.488Gbps data and to TTL high for 2.67Gbps data.
6
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Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC
Pin Description (continued)
PIN 10 11 12 13 14 15 16 17, 20 18 19 EP NAME SCLKEN SCLKOSCLKO+ VCC_BUF SDOSDO+ LOL GND FILFIL+ Exposed Pad FUNCTION Clock Output Enable, TTL Input. When SCLKEN = OPEN or SCLKEN = High, the clock outputs (SCLKO) are enabled. When SCLKEN = Low, the clock outputs are disabled and SCLKO = VCC. Negative Clock Output, CML. This output can be disabled by setting SCLKEN to Low. Positive Clock Output, CML. This output can be disabled by setting SCLKEN to Low. 3.3V CML Output Buffer Supply Voltage Negative Data Output, CML Positive Data Output, CML Loss-of-Lock Output, TTL (Active-Low). The LOL output indicates a PLL lock failure. Supply Ground Negative PLL Loop Filter Connection. Connect a 0.01F capacitor between FIL+ and FIL-. Positive PLL Loop Filter Connection. Connect a 0.01F capacitor between FIL+ and FIL-. Ground. The exposed pad must be soldered to the circuit board ground for proper electrical and thermal operation.
MAX3873
Detailed Description
The MAX3873 consists of a fully integrated phaselocked loop (PLL), input amplifier, and CML output buffers (Figure 5). The PLL consists of a phase/frequency detector, a loop filter, and a voltage-controlled oscillator (VCO). This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully-differential signal architecture and low-noise design techniques.
Input Amplifier
The input amplifier provides internal 50 line terminations and can accept a differential input amplitude from 50mV P-P to 1600mV P-P . The structure of the input amplifier is shown in Figure 9.
Phase Detector
The phase detector incorporated in the MAX3873 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming.
Frequency Detector
VCC GND FIL+ FILRATESET
SDO+ AMP
MAX3873
SDOMODE
SDI+ AMP SDIPHASE AND FREQUENCY DETECTOR LOOP FILTER VCO Q SCLKEN LOL I SCLKO+ AMP SCLKO-
The digital frequency detector (FD) aids frequency acquisition during startup conditions. The frequency difference between the received data and the VCO clock is derived by sampling the VCO outputs on each edge of the data input signal. The FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state.
Loop Filter and VCO
The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor, CF, is required to set the PLL damping ratio. See the Design Procedure section for guidelines on selecting this capacitor.
FASTRACK
Figure 5. Functional Diagram
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7
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873
The loop filter output controls the on-chip LC VCO running at either 2.488GHz or 2.67GHz. The VCO provides low phase noise and is trimmed to the correct frequency. Clock jitter generation is typically 2psRMS within a jitter band of 12kHz to 20MHz. For example, using CF = 2000pF results in jitter peaking of 0.2dB. Reducing CF below 500pF might result in PLL instability. The recommended value is CF = 0.01F to guarantee a maximum jitter peaking of less than 0.1dB. CF must be a low TC, high-quality capacitor of type X7R or better.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is incorporated in the MAX3873 to indicate either a loss of frequency lock or the absence of incoming data. Under loss of lock conditions, LOL may momentarily assert high due to noise.
FASTRACK Mode
The MAX3873 has a PLL fast-track (FASTRACK) mode to decrease locking time in switched data applications. In applications where the input data is switched from one source to another, there is a brief period where there is no valid data input to the MAX3873. In the absence of input data, the PLL phase will slowly drift from the ideal position. By enabling FASTRACK during reacquisition, the time required to regain phase alignment is reduced. This is accomplished by increasing the loop bandwidth by approximately 50%. The bandwidth of the MAX3873 is also linearly dependent upon the transition density of the input data. By using a preamble of 1200 bits of a 1-0 pattern during switching, the loop bandwidth is increased by a factor of approximately 2 (see Figure 3). Thus by using a 1-0 pattern preamble and enabling FASTRACK, the PLL bandwidth is increased by a factor of approximately 3, resulting in the fastest possible reacquisition of phase lock. FASTRACK increases the rate at which the MAX3873 acquires the proper phase, assuming that the VCO is already running at the proper frequency. On startup conditions, however, the VCO frequency is significantly different from the input data, and the time required to lock to the incoming data is increased to approximately 1.0ms.
Design Procedure
Setting the Loop Filter
The MAX3873 is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (JBW) below 2.0MHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF, and can be approximated according to: fz = 1 2 (3000) CF
with CF expressed in F. For an overdamped system, the jitter peaking (JP) of a second-order system can be approximated by: fz JP = 20 log 1 + JBW
HO(j2f) (dB)
H(j2f) (dB) CF = 2000pF 0 CLOSED-LOOP GAIN
OPEN-LOOP GAIN
-3
CF = 0.01F
CF = 0.01F fZ = 5.3kHz
CF = 2000pF fZ = 26kHz
f (kHz) 1 10 100 1000 1 10 100 1000
f (kHz)
Figure 6. Open-Loop Transfer Function
Figure 7. Closed-Loop Transfer Function
8
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Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC
Sinusoidal Jitter Tolerance and Input Deterministic Jitter Trade-Offs
The MAX3873 has excellent jitter tolerance. Adding DJ to the input will close the eye opening and result in reduced sinusoidal jitter tolerance. It typically can tolerate more than 0.3UIP-P of 10MHz jitter when measured with a 223 - 1 PRBS data stream with 0.4UI of deterministic jitter (DJ). This gives a total high-frequency jitter tolerance of 0.7UI. Refer to the Jitter Tolerance vs. Pulse-Width Distortion and Jitter Tolerance vs. Deterministic Jitter graphs in the Typical Operating Characteristics section.
Applications Information
Consecutive Identical Digits (CID)
The MAX3873 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of less than 10-10. The CID tolerance is tested using a 213 - 1 PRBS, substituting a long run of zeros to simulate the worst case. A CID tolerance of 2000 bits is typical.
MAX3873
Exposed-Pad Package
The exposed-pad (EP), 20-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3873 and must be soldered to the circuit board for proper thermal and electrical performance.
Input and Output Terminations
The MAX3873's digital CML outputs (SDO+, SDO-, SCLKO+, SCLKO-) have selectable output amplitude controlled by the MODE input. If the SCLKO outputs are not used, they can be disabled (see the Supply Current vs. Temperature graph in the Typical Operating Characteristics section). The structure of the high-speed digital outputs is shown in Figure 8. The MODE input sets the current in the current source, thereby controlling the output swing. The SCLKEN input sets the current in the SCLKO current source to 0mA, disabling the output. The structure of the CML inputs (SDI) is shown in Figure 9. Unless the CML input is DC-coupled to a CML output, use AC-coupling with the CML inputs to avoid upsetting the common-mode voltage.
Layout
Circuit board layout and design can significantly affect the MAX3873's performance. Use good high-frequency design techniques, including minimizing ground inductance and using controlled-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to the VCC pins as possible. Isolate the input from the output signals to reduce feedthrough.
VCC
MAX3873
VCC
VCC
50
50
50
SDI+
OUT+
OUT-
VCC
50 SDI-
MODE
SCLKO ONLY
SCLKEN
MAX3873
Figure 8. CML Output Model
Figure 9. CML Input Model 9
_______________________________________________________________________________________
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873
Typical Application Circuit
SWITCH CARD
2.5Gbps OPTICAL TRANSCEIVER
MAX3873
CDR
CROSSPOINT SWITCH
SDI+ SDI-
FIL+
FIL-
LOL
MODE
MAX3873
FASTRACK RATESET 20-PIN QFN
SDO+ SDOSCLKO+ SCLKOSCLKEN
Chip Information
TRANSISTOR COUNT: 2028 PROCESS: SiGe BiCMOS
10
______________________________________________________________________________________
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12,16,20, 24L QFN.EPS
MAX3873
PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM
21-0106
E
1
2
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11
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM
21-0106
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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